555 search results - page 94 / 111 » Efficient event-driven simulation of parallel processor arch... |
SIGARCH
2008
13 years 7 months ago
2008
As multicore architectures gain widespread use, it becomes increasingly important to be able to harness their additional processing power to achieve higher performance. However, e...
HPCA
2008
IEEE
14 years 8 months ago
2008
IEEE
This paper describes a comprehensive approach for using the memory controller to improve DRAM energy efficiency and manage DRAM power. We make three contributions: (1) we describe...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
Hybrid chip multithreaded SMPs present new challenges as well as new opportunities to maximize performance. Our intention is to discover the optimal operating configuration of suc...
IPPS
1998
IEEE
13 years 12 months ago
1998
IEEE
In the study of PetaFlop project, Processor-In-Memory array was proposed to be a target architecture in achieving 1015 floating point operations per second computing performance. ...
SPAA
2000
ACM
13 years 11 months ago
2000
ACM
Modern VLSI processing supports a two-dimensional surface for active devices along with multiple stacked layers of interconnect. With the advent of planarization, the number of la...