120 search results - page 13 / 24 » Efficient hardware code generation for FPGAs |
IEEEPACT
2003
IEEE
14 years 25 days ago
2003
IEEE
Effective modeling and management of hardware resources have always been critical toward generating highly efficient code in static compilers. With Just-In-Time compilation and dy...
CSREAESA
2008
13 years 9 months ago
2008
A group testing-based BIST technique to identify faulty hard cores in FPGA devices is presented. The method provides for isolation of faults in embedded cores as demonstrated by ex...
RSP
1999
IEEE
13 years 11 months ago
1999
IEEE
SDL is currently gaining interest as a system level specification language for HW/SW codesign. Automated synthesis of SDL in hardware so far had problems with its efficiency. The ...
FPL
2009
Springer
14 years 5 days ago
2009
Springer
Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor...
TCAD
2008
13 years 7 months ago
2008
Abstract--Multimedia and DSP applications have several computationally intensive kernels which are often offloaded and accelerated by application-specific hardware. This paper pres...