120 search results - page 22 / 24 » Efficient hardware code generation for FPGAs |
APCSAC
2001
IEEE
13 years 11 months ago
2001
IEEE
In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded micropro...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
This article outlines several projects aimed at generating electrical energy by passively tapping a variety of human body sources and activities. After summarizing different energ...
IEEEPACT
2002
IEEE
14 years 13 days ago
2002
IEEE
Java exception checks are designed to ensure that any faulting instruction causing a hardware exception does not terminate the program abnormally. These checks, however, impose so...
IEEEINTERACT
2003
IEEE
14 years 24 days ago
2003
IEEE
This paper introduces a method for improving program run-time performance by gathering work in an application and executing it efficiently in an integrated thread. Our methods ext...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
For successful SoC design, efficient and scalable communication architecture is crucial. Some bus interconnects now provide configurable structures to meet this requirement of an ...