391 search results - page 4 / 79 » Efficient inductance extraction using circuit-aware techniqu... |
DAC
2005
ACM
13 years 9 months ago
2005
ACM
Spatially distributed 3D circuit models are extracted with a segmentto-segment BEM (Boundary Element Method) algorithm for both capacitance and inverse inductance couplings rather...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
The simulation of on-chip inductance using PEEC-based circuit analysis methods often requires the solution of a subproblem where an extracted inductance matrix must be multiplied ...
TVLSI
2002
13 years 7 months ago
2002
Abstract--The design of high integrity, area efficient power distribution grids has become of practical importance as the portion of on-chip interconnect resources dedicated to pow...
HIPC
2004
Springer
14 years 1 months ago
2004
Springer
Parasitic extraction techniques are used to estimate signal delay in VLSI chips. Inductance extraction is a critical component of the parasitic extraction process in which on-chip ...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
A mixed potential integral equation (MPIE) technique combined with fast multi-layer Green’s functions and Gaussian Jacobi high order techniques is used to compute the 3-D freque...