Sciweavers

47 search results - page 1 / 10
» Efficient instruction schedulers for SMT processors
Sort
View
HPCA
2006
IEEE
14 years 7 months ago
Efficient instruction schedulers for SMT processors
We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently propos...
Joseph J. Sharkey, Dmitry V. Ponomarev
HPCA
2008
IEEE
14 years 7 months ago
PEEP: Exploiting predictability of memory dependences in SMT processors
Simultaneous Multithreading (SMT) attempts to keep a dynamically scheduled processor's resources busy with work from multiple independent threads. Threads with longlatency st...
Samantika Subramaniam, Milos Prvulovic, Gabriel H....
RTSS
2002
IEEE
14 years 10 days ago
Soft Real- Time Scheduling on Simultaneous Multithreaded Processors
Simultaneous multithreading (SMT) improves processor throughput by processing instructions from multiple threads each cycle. This is the first work to explore soft real-time sche...
Rohit Jain, Christopher J. Hughes, Sarita V. Adve
IEEEPACT
2006
IEEE
14 years 1 months ago
Adaptive reorder buffers for SMT processors
In SMT processors, the complex interplay between private and shared datapath resources needs to be considered in order to realize the full performance potential. In this paper, we...
Joseph J. Sharkey, Deniz Balkan, Dmitry Ponomarev
CF
2004
ACM
14 years 26 days ago
Predictable performance in SMT processors
Current instruction fetch policies in SMT processors are oriented towards optimization of overall throughput and/or fairness. However, they provide no control over how individual ...
Francisco J. Cazorla, Peter M. W. Knijnenburg, Riz...