Sciweavers

47 search results - page 3 / 10
» Efficient instruction schedulers for SMT processors
Sort
View
TSP
2008
123views more  TSP 2008»
13 years 7 months ago
A Rough Programming Approach to Power-Balanced Instruction Scheduling for VLIW Digital Signal Processors
The focus of this paper is on VLIW instruction scheduling that minimizes the variation of power consumed by the processor during the execution of a target program. We use rough set...
Shu Xiao, Edmund Ming-Kit Lai
ISCAPDCS
2004
13 years 8 months ago
An Adaptive OpenMP Loop Scheduler for Hyperthreaded SMPs
Hyperthreaded(HT) and simultaneous multithreaded (SMT) processors are now available in commodity workstations and servers. This technology is designed to increase throughput by ex...
Yun Zhang, Mihai Burcea, Victor Cheng, Ron Ho, Mic...
ICCD
2005
IEEE
108views Hardware» more  ICCD 2005»
14 years 4 months ago
Methods for Modeling Resource Contention on Simultaneous Multithreading Processors
Simultaneous multithreading (SMT) seeks to improve the computation throughput of a processor core by sharing primary resources such as functional units, issue bandwidth, and cache...
Tipp Moseley, Dirk Grunwald, Joshua L. Kihm, Danie...
HPCA
2008
IEEE
14 years 7 months ago
Runahead Threads to improve SMT performance
In this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded...
Tanausú Ramírez, Alex Pajuelo, Olive...
GECCO
2009
Springer
192views Optimization» more  GECCO 2009»
13 years 5 months ago
Improving SMT performance: an application of genetic algorithms to configure resizable caches
Simultaneous Multithreading (SMT) is a technology aimed at improving the throughput of the processor core by applying Instruction Level Parallelism (ILP) and Thread Level Parallel...
Josefa Díaz, José Ignacio Hidalgo, F...