47 search results - page 9 / 10 » Efficient instruction schedulers for SMT processors |
RTSS
1998
IEEE
13 years 11 months ago
1998
IEEE
The energy efficiency of systems-on-a-chip can be much improved if one were to vary the supply voltage dynamically at run time. In this paper we describe the synthesis of systems-...
ASAP
2004
IEEE
13 years 11 months ago
2004
IEEE
We describe a general-purpose processor architecture for accelerating public-key computations on server systems that demand high performance and flexibility to accommodate large n...
TCAD
2002
13 years 7 months ago
2002
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...
CLUSTER
2007
IEEE
14 years 1 months ago
2007
IEEE
— The Cell Broadband Engine (BE) is a heterogeneous multicore processor, combining a general-purpose POWER architecture core with eight independent single-instructionmultiple-dat...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
Modern embedded CPU systems rely on a growing number of software features, but this growth increases the memory footprint and increases the need for efficient instruction and data...