258 search results - page 2 / 52 » Efficient memory simulation in SimICS |
DATE
2003
IEEE
14 years 27 days ago
2003
IEEE
This paper introduces an efficient multithreaded synchronous dataflow (SDF) scheduler that can significantly reduce the running time of multi-rate SDF simulations on multiprocesso...
AINA
2007
IEEE
14 years 1 months ago
2007
IEEE
The widening gap between CPU and memory speed has made caches an integral feature of modern highperformance processors. The high degree of configurability of cache memory can requ...
ISCA
1999
IEEE
13 years 12 months ago
1999
IEEE
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
ICMCS
2005
IEEE
14 years 1 months ago
2005
IEEE
The paper presents a high-performance architecture of the bit-plane coder for the embedded block coding algorithm in JPEG 2000. The architecture adopts a pipeline structure and is...
CODES
2005
IEEE
14 years 1 months ago
2005
IEEE
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...