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» Efficient simplex computation for fixture layout design
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SPAA
2000
ACM
13 years 11 months ago
Compact, multilayer layout for butterfly fat-tree
Modern VLSI processing supports a two-dimensional surface for active devices along with multiple stacked layers of interconnect. With the advent of planarization, the number of la...
André DeHon
ICPR
2000
IEEE
14 years 8 months ago
Automatic Training of Page Segmentation Algorithms: An Optimization Approach
Most page segmentation algorithms have userspecifiable free parameters. However, algorithm designers typically do not provide a quantitative/rigorous method for choosing values fo...
Song Mao, Tapas Kanungo
GRAPHICSINTERFACE
2009
13 years 5 months ago
Sketch-based path design
We present Drive, a system for the conceptual layout of 3D path networks. Our sketch-based interface allows users to efficiently author path layouts with minimal instruction. Our ...
James McCrae, Karan Singh
ICCAD
2009
IEEE
136views Hardware» more  ICCAD 2009»
13 years 5 months ago
A hierarchical floating random walk algorithm for fabric-aware 3D capacitance extraction
With the adoption of ultra regular fabric paradigms for controlling design printability at the 22nm node and beyond, there is an emerging need for a layout-driven, pattern-based p...
Tarek A. El-Moselhy, Ibrahim M. Elfadel, Luca Dani...
FPL
2010
Springer
148views Hardware» more  FPL 2010»
13 years 5 months ago
FEM: A Step Towards a Common Memory Layout for FPGA Based Accelerators
FPGA devices are mostly utilized for customized application designs with heavily pipelined and aggressively parallel computations. However, little focus is normally given to the FP...
Muhammad Shafiq, Miquel Pericàs, Nacho Nava...