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» Efficient simulation of critical synchronous dataflow graphs
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ICASSP
2010
IEEE
13 years 7 months ago
Buffer management for multi-application image processing on multi-core platforms: Analysis and case study
Due to the limited amounts of on-chip memory, large volumes of data, and performance and power consumption overhead associated with interprocessor communication, efficient managem...
Dong-Ik Ko, Nara Won, Shuvra S. Bhattacharyya
MST
2002
169views more  MST 2002»
13 years 7 months ago
Bulk Synchronous Parallel Algorithms for the External Memory Model
Abstract. Blockwise access to data is a central theme in the design of efficient external memory (EM) algorithms. A second important issue, when more than one disk is present, is f...
Frank K. H. A. Dehne, Wolfgang Dittrich, David A. ...
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
14 years 1 months ago
Pre-synthesis optimization of multiplications to improve circuit performance
Conventional high-level synthesis uses the worst case delay to relate all inputs to all outputs of an operation. This is a very conservative approximation of reality, especially i...
Rafael Ruiz-Sautua, María C. Molina, Jos&ea...
CJ
1999
87views more  CJ 1999»
13 years 7 months ago
Evolution-Based Scheduling of Computations and Communications on Distributed Memory Multicomputers
We present a compiler optimization approach that uses the simulated evolution (SE) paradigm to enhance the finish time of heuristically scheduled computations with communication t...
Mayez A. Al-Mouhamed
CRV
2008
IEEE
183views Robotics» more  CRV 2008»
14 years 2 months ago
Robust Real-Time Bi-Layer Video Segmentation Using Infrared Video
In this paper, we propose a novel method for the automatic segmentation of a foreground layer from a natural scene in real time by fusing infrared, color and edge information. Thi...
Qiong Wu, Pierre Boulanger, Walter F. Bischof