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TVLSI
2010
13 years 4 months ago
LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
Deming Chen, Jason Cong, Yiping Fan, Lu Wan
ECCV
2002
Springer
14 years 12 months ago
Implicit Probabilistic Models of Human Motion for Synthesis and Tracking
Abstract. This paper addresses the problem of probabilistically modeling 3D human motion for synthesis and tracking. Given the high dimensional nature of human motion, learning an ...
Hedvig Sidenbladh, Michael J. Black, Leonid Sigal
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
14 years 2 months ago
Hardware Synthesis from C/C++ Models
Software programming languages, such as C/C++, have been used as means for specifying hardware for quite a while. Different design methodologies have exploited the advantages of f...
Giovanni De Micheli
SP
2000
IEEE
14 years 1 months ago
Searching for a Solution: Engineering Tradeoffs and the Evolution of Provably Secure Protocols
Tradeoffs are an important part of engineering security. Protocol security is important. So are efficiency and cost. This paper provides an early framework for handling such aspec...
John A. Clark, Jeremy L. Jacob
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 7 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...