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VLSID
2005
IEEE
285views VLSI» more  VLSID 2005»
14 years 7 months ago
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan,...
JRTIP
2008
249views more  JRTIP 2008»
13 years 6 months ago
Model-based mapping of reconfigurable image registration on FPGA platforms
Abstract Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficie...
Mainak Sen, Yashwanth Hemaraj, William Plishker, R...
TECS
2008
122views more  TECS 2008»
13 years 6 months ago
Quantitative analysis of the speed/accuracy trade-off in transaction level modeling
tion. Transaction Level Modeling (TLM) has been proposed to abstract communication for highspeed system simulation and rapid design space exploration. Although being widely accepte...
Gunar Schirner, Rainer Dömer
DAC
2006
ACM
13 years 8 months ago
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...
David Atienza, Pablo Garcia Del Valle, Giacomo Pac...
FMICS
2006
Springer
13 years 10 months ago
Can Saturation Be Parallelised?
Abstract. Symbolic state-space generators are notoriously hard to parallelise. However, the Saturation algorithm implemented in the SMART verification tool differs from other seque...
Jonathan Ezekiel, Gerald Lüttgen, Radu Simini...