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MTV
2007
IEEE
118views Hardware» more  MTV 2007»
15 years 8 months ago
Reduction of Power Dissipation during Scan Testing by Test Vector Ordering
Test vector ordering is recognized as a simple and non-intrusive approach to assist test power reduction. Simulation based test vector ordering approach to minimize circuit transit...
Wang-Dauh Tseng, Lung-Jen Lee
VTS
2000
IEEE
126views Hardware» more  VTS 2000»
15 years 6 months ago
Static Compaction Techniques to Control Scan Vector Power Dissipation
Excessive switching activity during scan testing can cause average power dissipation and peak power during test to be much higher than during normal operation. This can cause prob...
Ranganathan Sankaralingam, Rama Rao Oruganti, Nur ...
EUROSYS
2008
ACM
15 years 11 months ago
Task activity vectors: a new metric for temperature-aware scheduling
Non-uniform utilization of functional units in combination with hardware mechanisms such as clock gating leads to different power consumptions in different parts of a processor ch...
Andreas Merkel, Frank Bellosa
ISVLSI
2007
IEEE
181views VLSI» more  ISVLSI 2007»
15 years 8 months ago
Code-coverage Based Test Vector Generation for SystemC Designs
Abstract— Time-to-Market plays a central role on System-ona-Chip (SoC) competitiveness and the quality of the final product is a matter of concern as well. As SoCs complexity in...
Alair Dias Jr., Diógenes Cecilio da Silva J...
VISUALIZATION
2003
IEEE
15 years 7 months ago
Chameleon: An interactive texture-based rendering framework for visualizing three-dimensional vector fields
In this paper we present an interactive texture-based technique for visualizing three-dimensional vector fields. The goal of the algorithm is to provide a general volume renderin...
Guo-Shi Li, Udeepta Bordoloi, Han-Wei Shen