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DATE
2007
IEEE
150views Hardware» more  DATE 2007»
14 years 5 months ago
A low-SER efficient core processor architecture for future technologies
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
ICMCS
2005
IEEE
104views Multimedia» more  ICMCS 2005»
14 years 4 months ago
A High-Performance Memory-Efficient Architecture of the Bit-Plane Coder in JPEG 2000
The paper presents a high-performance architecture of the bit-plane coder for the embedded block coding algorithm in JPEG 2000. The architecture adopts a pipeline structure and is...
Grzegorz Pastuszak
SAMOS
2004
Springer
14 years 4 months ago
Synchronous Transfer Architecture (STA)
This paper presents a novel micro-architecture for high-performance and low-power DSPs. The underlying Synchronous Transfer Architecture (STA) fills the gap between SIMD-DSPs and ...
Gordon Cichon, Pablo Robelly, Hendrik Seidel, Emil...
ERSHOV
2006
Springer
14 years 2 months ago
An Agent-Based Architecture for Dialogue Systems
Abstract. Research in dialogue systems has been moving towards reusable and adaptable architectures for managing dialogue execution and integrating heterogeneous subsystems. In thi...
Mark Buckley, Christoph Benzmüller
CSE
2009
IEEE
14 years 5 months ago
Prospector: Multiscale Energy Measurement of Networked Embedded Systems with Wideband Power Signals
Abstract—Today’s wirelessly networked embedded systems underlie a vast array of electronic devices, performing computation, communication, and input/output. A major design goal...
Kenji R. Yamamoto, Paul G. Flikkema