Sciweavers

1742 search results - page 109 / 349
» Embedded MPLS Architecture
Sort
View
ASPDAC
2000
ACM
92views Hardware» more  ASPDAC 2000»
15 years 7 months ago
Co-synthesis with custom ASICs
- This paper introduces the first hardwarekoftware co-synthesis algorithm that optimizes the implementations of ASICs that are used as processing elements for the embedded systems....
Yuan Xie, Wayne Wolf
ECRTS
2004
IEEE
15 years 6 months ago
Schedulability-Driven Partitioning and Mapping for Multi-Cluster Real-Time Systems
We present an approach to partitioning and mapping for multicluster embedded systems consisting of time-triggered and eventtriggered clusters, interconnected via gateways. We have...
Paul Pop, Petru Eles, Zebo Peng, Viacheslav Izosim...
DAC
2005
ACM
16 years 4 months ago
Improving java virtual machine reliability for memory-constrained embedded systems
Dual-execution/checkpointing based transient error tolerance techniques have been widely used in the high-end mission critical systems. These techniques, however, are not very att...
Guangyu Chen, Mahmut T. Kandemir
VLSID
2003
IEEE
123views VLSI» more  VLSID 2003»
16 years 3 months ago
Synthesis of Real-Time Embedded Software by Timed Quasi-Static Scheduling
A formal synthesis method for complex real-time embedded software is proposed in this work. Compared to previous work, our method not only synthesizes embedded software with compl...
Pao-Ann Hsiung, Feng-Shi Su
ICCAD
2006
IEEE
111views Hardware» more  ICCAD 2006»
16 years 1 days ago
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs
This work describes a new mapping technique, RAM-MAP, that identifies parts of circuits that can be efficiently mapped into the synchronous embedded memories found on field prog...
Gordon R. Chiu, Deshanand P. Singh, Valavan Manoha...