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DAC
2011
ACM
12 years 9 months ago
Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect
Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation te...
Jim Aarestad, Charles Lamech, Jim Plusquellic, Dhr...
VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
14 years 9 months ago
Customization of Register File Banking Architecture for Low Power
Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application s...
Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda
SBACPAD
2009
IEEE
155views Hardware» more  SBACPAD 2009»
14 years 4 months ago
SPARC16: A New Compression Approach for the SPARC Architecture
RISC processors can be used to face the ever increasing demand for performance required by embedded systems. Nevertheless, this solution comes with the cost of poor code density. ...
Leonardo Luiz Ecco, Bruno Cardoso Lopes, Eduardo C...
HICSS
2008
IEEE
121views Biometrics» more  HICSS 2008»
14 years 3 months ago
An Integrated Architecture for Demand Response Communications and Control
1 In the competitive electricity structure, demand response programs enable customers to react dynamically to changes in electricity prices. The implementation of such programs ma...
Michael LeMay, Rajesh Nelli, George Gross, Carl A....
GLOBECOM
2007
IEEE
14 years 3 months ago
Secure Key Management Architecture Against Sensor-Node Fabrication Attacks
Abstract—In lightweight mobile ad hoc networks, both probabilistic and deterministic key management schemes are fragile to node fabrication attacks. Our simulation results show t...
Jeffrey S. Dwoskin, Dahai Xu, Jianwei Huang, Mung ...