Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect

Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation techniques to reduce the detrimental effects of delay variations, particularly those that occur within-die, new methods of measuring delay variations within actual products are needed. The data provided by such techniques can also be used for validating models, i.e., can assist with model-to-hardware correlation. In this paper, we propose a flush delay technique for measuring both regional delay variations and SOI history effect and validate the method using a test structure fabricated in a 65 nm SOI process. Categories and Subject Descriptors B.8.2[Hardware]:Performance and Reliability - Performance Analysis and Design Aids General Terms Experimentation Keywords Embedded Test Structure, Design for Manufacturability

• Type: Journal
• Year: 2011
• Where: DAC
• Authors: Jim Aarestad, Charles Lamech, Jim Plusquellic, Dhruva Acharyya, Kanak Agarwal
• Keywords: Computer Architecture, DAC 2011, Design Aids, Mitigation Techniques, Test Structure