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ICDCS
2002
IEEE
14 years 2 months ago
ControlWare: A Middleware Architecture for Feedback Control of Software Performance
Attainment of software performance assurances in open, largely unpredictable environments has recently become an important focus for real-time research. Unlike closed embedded sys...
Ronghua Zhang, Chenyang Lu, Tarek F. Abdelzaher, J...
MSE
2000
IEEE
174views Hardware» more  MSE 2000»
14 years 1 months ago
Integrating a Digital Camera in the Home Environment: Architecture and Prototype
Electronic photography is gaining parts of the photography market and tends to replace gradually all argentic photography. The combination of digital camera and computer technolog...
Nadia Bennani
ISLPED
1996
ACM
103views Hardware» more  ISLPED 1996»
14 years 1 months ago
A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving
This paper proposes a 0.5V / 100MHz / sub-5mW-operated 1-Mbit SRAM cell architecture which uses an overVCC grounded data storage (OVGS) scheme. The key target of OVGS is to minimi...
Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, ...
AHS
2007
IEEE
239views Hardware» more  AHS 2007»
14 years 1 months ago
Separation of Data flow and Control flow in Reconfigurable Multi-core SoCs using the Gannet Service-based Architecture
This paper presents a mechanism for the separation of control and data flow in NoC-based SoCs consisting of multiple heterogeneous reconfigurable IP cores. This mechanism enables ...
Wim Vanderbauwhede
ICCD
2007
IEEE
105views Hardware» more  ICCD 2007»
14 years 1 months ago
Power-aware mapping for reconfigurable NoC architectures
A core mapping method for reconfigurable network-on-chip (NoC) architectures is presented in this paper. In most of the existing methods, mapping is carried out based on the traff...
Mehdi Modarressi, Hamid Sarbazi-Azad