823 search results - page 101 / 165 » Embedded Robustness Ips |
ICCAD
2001
IEEE
14 years 5 months ago
2001
IEEE
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
CISIS
2009
IEEE
2009
IEEE
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints
14 years 3 months ago
—Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them a...
ETS
2006
IEEE
14 years 3 months ago
2006
IEEE
The Networks-on-Chip (NoCs) paradigm is emerging as a solution for the communication of SoCs. Many NoC architecture propositions are presented but few works on testing these netwo...
IPPS
2006
IEEE
14 years 3 months ago
2006
IEEE
Modern FPGA platforms provide the hardware and software infrastructure for building a bus-based System on Chip (SoC) that meet the applications requirements. The designer can cust...
FDL
2005
IEEE
14 years 2 months ago
2005
IEEE
Embedded system designs and simulations become tedious and time consuming due to the complexity of modern applications. Thus, languages allowing high level description, such as Sy...