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» Embedded System Design for Network Time Synchronization
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DATE
2005
IEEE
110views Hardware» more  DATE 2005»
15 years 8 months ago
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
The increasing complexity and the short life cycles of embedded systems are pushing the current system-onchip designs towards a rapid increasing on the number of programmable proc...
Alexandre M. Amory, Marcelo Lubaszewski, Fernando ...
GLOBECOM
2010
IEEE
15 years 15 days ago
Mobi-Sync: Efficient Time Synchronization for Mobile Underwater Sensor Networks
Abstract--Time synchronization is a critical service for distributed network systems. In this work, we investigate this problem in the context of underwater sensor networks (UWSNs)...
Jun Liu, Robert Zhong Zhou, James Peng Zheng, Jun-...
RTAS
2009
IEEE
15 years 9 months ago
The System-Level Simplex Architecture for Improved Real-Time Embedded System Safety
Embedded systems in safety-critical environments demand safety guarantees while providing many useful services that are too complex to formally verify or fully test. Existing appl...
Stanley Bak, Deepti K. Chivukula, Olugbemiga Adeku...
143
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DATE
2009
IEEE
126views Hardware» more  DATE 2009»
15 years 9 months ago
Integrated scheduling and synthesis of control applications on distributed embedded systems
Many embedded control systems comprise several control loops that are closed over a network of computation nodes. In such systems, complex timing behavior and communication lead t...
Soheil Samii, Anton Cervin, Petru Eles, Zebo Peng
ISSS
2000
IEEE
144views Hardware» more  ISSS 2000»
15 years 7 months ago
Efficient Hardware Controller Synthesis for Synchronous Dataflow Graph in System Level Design
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification in system level design. In the presented design methodology, each node of a data flow gra...
Hyunuk Jung, Kangnyoung Lee, Soonhoi Ha