26 search results - page 4 / 6 » Employing Register Channels for the Exploitation of Instruct... |
VLSID
2004
IEEE
14 years 7 months ago
2004
IEEE
With increasing demands for high performance by embedded systems, especially by digital signal processing applications, embedded processors must increase available instruction lev...
HPCA
2003
IEEE
14 years 7 months ago
2003
IEEE
To continue to improve processor performance, microarchitects seek to increase the effective instruction level parallelism (ILP) that can be exploited in applications. A fundament...
ICDCS
2010
IEEE
13 years 11 months ago
2010
IEEE
—Transmission power plays a crucial role in the design and performance of wireless networks. The issue is therefore complex since an increase in transmission power implies that a...
SC
1992
ACM
13 years 11 months ago
1992
ACM
Exploiting parallelism at both the multiprocessor level and the instruction level is an e ective means for supercomputers to achieve high-performance. The amount of instruction-le...
IISWC
2009
IEEE
14 years 2 months ago
2009
IEEE
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...