30 search results - page 4 / 6 » Enabling Large-Scale Multicast Simulation by Reducing Memory... |
DAC
2004
ACM
14 years 8 months ago
2004
ACM
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
VALUETOOLS
2006
ACM
14 years 1 months ago
2006
ACM
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
ASPLOS
2009
ACM
14 years 2 months ago
2009
ACM
This paper explores the architectural implications of integrating computation and molecular probes to form nanoscale sensor processors (nSP). We show how nSPs may enable new compu...
ISCA
1994
IEEE
13 years 11 months ago
1994
IEEE
Today's commodity microprocessors require a low latency memory system to achieve high sustained performance. The conventional high-performance memory system provides fast dat...
ISCA
2000
IEEE
13 years 11 months ago
2000
IEEE
Communication in cache-coherent distributed shared memory (DSM) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. This paper...