Sciweavers

6 search results - page 1 / 2
» Enabling compiler flow for embedded VLIW DSP processors with...
Sort
View
LCTRTS
2007
Springer
14 years 29 days ago
Enabling compiler flow for embedded VLIW DSP processors with distributed register files
High-performance and low-power VLIW DSP processors are increasingly deployed on embedded devices to process video and multimedia applications. For reducing power and cost in desig...
Chung-Kai Chen, Ling-Hua Tseng, Shih-Chang Chen, Y...
RTCSA
2006
IEEE
14 years 25 days ago
Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors
To support high-performance and low-power for multimedia applications and for hand-held devices, embedded VLIW DSP processors are of research focus. With the tight resource constr...
Chi Wu, Kun-Yuan Hsieh, Yung-Chia Lin, Chung-Ju Wu...
VLSISP
2008
159views more  VLSISP 2008»
13 years 6 months ago
Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores
The compiler is generally regarded as the most important software component that supports a processor design to achieve success. This paper describes our application of the open re...
Yung-Chia Lin, Chia-Han Lu, Chung-Ju Wu, Chung-Lin...
ASPDAC
2008
ACM
89views Hardware» more  ASPDAC 2008»
13 years 8 months ago
Load scheduling: Reducing pressure on distributed register files for free
In this paper we describe load scheduling, a novel method that balances load among register files by residual resources. Load scheduling can reduce register pressure for clustered...
Mei Wen, Nan Wu, Maolin Guan, Chunyuan Zhang
TVLSI
2002
102views more  TVLSI 2002»
13 years 6 months ago
Low-power data forwarding for VLIW embedded architectures
In this paper, we propose a low-power approach to the design of embedded very long instruction word (VLIW) processor architectures based on the forwarding (or bypassing) hardware, ...
Mariagiovanna Sami, Donatella Sciuto, Cristina Sil...