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» Encoding Algorithms for Logic Synthesis
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FPGA
1992
ACM
176views FPGA» more  FPGA 1992»
15 years 6 months ago
Minimization of Permuted Reed-Muller Trees for Cellular Logic
The new family of Field Programmable Gate Arrays, CLI6000 from Concurrent Logic Inc realizes the truly Cellular Logic. It has been mainly designed for the realization of data path...
Li-Fei Wu, Marek A. Perkowski
VLDB
1990
ACM
143views Database» more  VLDB 1990»
15 years 6 months ago
Synthesizing Database Transactions
Database programming requires having the knowledge of database semantics both to maintain database integrity and to explore more optimization opportunities. Automated programming ...
Xiaolei Qian
ICCAD
1999
IEEE
84views Hardware» more  ICCAD 1999»
15 years 6 months ago
OPTIMISTA: state minimization of asynchronous FSMs for optimum output logic
The optimal state minimization problem is to select a reduced state machine having the best logic implementation over all possible state reductions and encodings. A recent algorit...
Robert M. Fuhrer, Steven M. Nowick
DAC
2003
ACM
16 years 3 months ago
On-chip logic minimization
While Boolean logic minimization is typically used in logic synthesis, logic minimization can be useful in numerous other applications. However, many of those applications, such a...
Roman L. Lysecky, Frank Vahid
ARVLSI
1995
IEEE
179views VLSI» more  ARVLSI 1995»
15 years 6 months ago
Algorithms for the optimal state assignment of asynchronous state machines
This paper presents a method for the optimal state assignment of asynchronous state machines. Unlike state assignment for synchronous state machines, state codes must be chosen ca...
Robert M. Fuhrer, Bill Lin, Steven M. Nowick