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MICRO
2010
IEEE
215views Hardware» more  MICRO 2010»
13 years 8 months ago
A Task-Centric Memory Model for Scalable Accelerator Architectures
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...
MEMOCODE
2008
IEEE
14 years 4 months ago
Static Deadlock Detection for the SHIM Concurrent Language
Concurrent programming languages are becoming mandatory with the advent of multi-core processors. Two major concerns in any concurrent program are data races and deadlocks. Each a...
Nalini Vasudevan, Stephen A. Edwards
PLDI
1993
ACM
14 years 1 months ago
Global Optimizations for Parallelism and Locality on Scalable Parallel Machines
Data locality is critical to achievinghigh performance on large-scale parallel machines. Non-local data accesses result in communication that can greatly impact performance. Thus ...
Jennifer-Ann M. Anderson, Monica S. Lam
TWC
2008
87views more  TWC 2008»
13 years 9 months ago
A token-based scheduling scheme for WLANs supporting voice/data traffic and its performance analysis
Most of the existing medium access control (MAC) protocols for wireless local area networks (WLANs) provide prioritized access by adjusting the contention window sizes or interfram...
Ping Wang, Weihua Zhuang
IEEEPACT
2009
IEEE
14 years 4 months ago
Soft-OLP: Improving Hardware Cache Performance through Software-Controlled Object-Level Partitioning
—Performance degradation of memory-intensive programs caused by the LRU policy’s inability to handle weaklocality data accesses in the last level cache is increasingly serious ...
Qingda Lu, Jiang Lin, Xiaoning Ding, Zhao Zhang, X...