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IPPS
2010
IEEE
13 years 5 months ago
Inter-block GPU communication via fast barrier synchronization
The graphics processing unit (GPU) has evolved from a fixedfunction processor with programmable stages to a programmable processor with many fixed-function components that deliver...
Shucai Xiao, Wu-chun Feng
FPL
2006
Springer
161views Hardware» more  FPL 2006»
13 years 11 months ago
Predictive Load Balancing for Interconnected FPGAs
A Field Programmable Gate Array (FPGA), when used as a platform for implementing special-purpose computing architectures, offers the potential for increased functional parallelism...
Jason D. Bakos, Charles L. Cathey, Allen Michalski
POPL
2002
ACM
14 years 8 months ago
Predicate abstraction for software verification
e Abstraction for Software Verification Cormac Flanagan Shaz Qadeer Compaq Systems Research Center 130 Lytton Ave, Palo Alto, CA 94301 Software verification is an important and di...
Cormac Flanagan, Shaz Qadeer
OSDI
2008
ACM
14 years 8 months ago
Gadara: Dynamic Deadlock Avoidance for Multithreaded Programs
Deadlock is an increasingly pressing concern as the multicore revolution forces parallel programming upon the average programmer. Existing approaches to deadlock impose onerous bu...
Manjunath Kudlur, Scott A. Mahlke, Stéphane...
3DPVT
2004
IEEE
125views Visualization» more  3DPVT 2004»
13 years 11 months ago
GPU-Assisted Z-Field Simplification
Height fields and depth maps which we collectively refer to as z-fields, usually carry a lot of redundant information and are often used in real-time applications. This is the rea...
Alexander Bogomjakov, Craig Gotsman