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DAC
2002
ACM
14 years 8 months ago
River PLAs: a regular circuit structure
A regular circuit structure called a River PLA and its reconfigurable version, Glacier PLA, are presented. River PLAs provide greater regularity than circuits implemented with sta...
Fan Mo, Robert K. Brayton
FPL
2004
Springer
101views Hardware» more  FPL 2004»
14 years 1 months ago
Automatic Creation of Reconfigurable PALs/PLAs for SoC
Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run -time reconfigurabil...
Mark Holland, Scott Hauck
ICCL
1998
IEEE
13 years 12 months ago
An Infrastructure for Profile-Driven Dynamic Recompilation
Dynamic optimization of computer programs can dramatically improve their performance on a variety of applications. This paper presents an efficient infrastructure for dynamic reco...
Robert G. Burger, R. Kent Dybvig
MEMOCODE
2010
IEEE
13 years 5 months ago
Compilation of imperative synchronous programs with refined clocks
To overcome over-synchronization in synchronous programs, we recently introduced clock refinement to our synchronous programming language Quartz. This extension basically allows p...
Mike Gemunde, Jens Brandt, Klaus Schneider
ANCS
2007
ACM
13 years 11 months ago
Ruler: high-speed packet matching and rewriting on NPUs
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
Tomas Hruby, Kees van Reeuwijk, Herbert Bos