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DSD
2005
IEEE
104views Hardware» more  DSD 2005»
14 years 4 months ago
Design of Transport Triggered Architecture Processors for Wireless Encryption
Transport Triggered Architecture (TTA) offers a costeffective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. In this pa...
Panu Hämäläinen, Jari Heikkinen, Ma...
DATE
2009
IEEE
106views Hardware» more  DATE 2009»
14 years 5 months ago
A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing
—The IEEE 802.15.4a amendment has introduced ultra-wideband impulse radio (UWB IR) as a promising physical layer for energy-efficient, low data rate communications. A critical p...
Christian Bachmann, Andreas Genser, Jos Hulzink, M...
MICRO
2010
IEEE
173views Hardware» more  MICRO 2010»
13 years 8 months ago
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
To extend the exponential performance scaling of future chip multiprocessors, improving energy efficiency has become a first-class priority. Single-chip heterogeneous computing ha...
Eric S. Chung, Peter A. Milder, James C. Hoe, Ken ...
CGO
2008
IEEE
14 years 5 months ago
Modulo scheduling for highly customized datapaths to increase hardware reusability
In the embedded domain, custom hardware in the form of ASICs is often used to implement critical parts of applications when performance and energy efficiency goals cannot be met ...
Kevin Fan, Hyunchul Park, Manjunath Kudlur, Scott ...
ICRA
2007
IEEE
171views Robotics» more  ICRA 2007»
14 years 5 months ago
Design and Development of the Long-Jumping "Grillo" Mini Robot
Abstract— This paper describes the design of a fast longjumping robot conceived to move in unstructured environments through simple feed-forward control laws. Despite the apparen...
Umberto Scarfogliero, Cesare Stefanini, Paolo Dari...