Sciweavers

358 search results - page 27 / 72
» Energy and Performance Models for Clocked and Asynchronous C...
Sort
View
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
14 years 29 days ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
INFOCOM
2006
IEEE
14 years 1 months ago
Analyzing the Energy-Latency Trade-Off During the Deployment of Sensor Networks
— The inherent trade-off between energy-efficiency and rapidity of event dissemination is characteristic for wireless sensor networks. Scarcity of energy renders it necessary fo...
Thomas Moscibroda, Pascal von Rickenbach, Roger Wa...
CN
2006
104views more  CN 2006»
13 years 7 months ago
Slot allocation schemes for delay sensitive traffic support in asynchronous wireless mesh networks
Heterogeneous multihop wireless networks such as wireless mesh networks consist of a set of resource-constrained mobile nodes that want to communicate with each other and a set of...
V. Vidhyashankar, B. S. Manoj, C. Siva Ram Murthy
INFOCOM
2005
IEEE
14 years 1 months ago
Gossip algorithms: design, analysis and applications
Abstract— Motivated by applications to sensor, peer-topeer and ad hoc networks, we study distributed asynchronous algorithms, also known as gossip algorithms, for computation and...
Stephen P. Boyd, Arpita Ghosh, Balaji Prabhakar, D...
ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
14 years 1 months ago
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
Liqun Cheng, Naveen Muralimanohar, Karthik Ramani,...