358 search results - page 8 / 72 » Energy and Performance Models for Clocked and Asynchronous C... |
ENTCS
2008
13 years 7 months ago
2008
This paper reports on the design of a test chip built to test a) a new latency insensitive network fabric protocol and circuits, b) a new synchronizer design, and c) how efficient...
MOBICOM
2012
ACM
11 years 10 months ago
2012
ACM
In this paper, we propose a novel clock calibration approach called FLIGHT, which leverages the fact that the fluorescent light intensity changes with a stable period that equals...
CSE
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Today’s wirelessly networked embedded systems underlie a vast array of electronic devices, performing computation, communication, and input/output. A major design goal...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
Dynamic voltage scaling (DVS) is a technique that varies the supply voltage and clock frequency based on the computation load to provide desired performance with the minimal amoun...
ASYNC
2004
IEEE
13 years 11 months ago
2004
IEEE
Register files of microprocessors have often been cited as performance bottlenecks and significant consumers of energy. The robust and modular nature of quasi-delay insensitive (Q...