223 search results - page 22 / 45 » Energy efficient co-scheduling in dynamically reconfigurable... |
ISMVL
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper, we propose three novel cache models using Multiple-Valued Logic (MVL) paradigm to reduce the cache data storage area and cache energy consumption for embedded syste...
DSRT
2008
IEEE
14 years 2 months ago
2008
IEEE
In the past decade parallel disk systems have been highly scalable and able to alleviate the problem of disk I/O bottleneck, thereby being widely used to support a wide range of d...
ICCAD
1998
IEEE
13 years 12 months ago
1998
IEEE
Presented in this paper are 1) information-theoretic lower bounds on energy consumption of noisy digital gates and 2) the concept of noise tolerance via coding for achieving energy...
VLSID
2004
IEEE
14 years 8 months ago
2004
IEEE
This paper presents a very efficient and versatile method to handle Dynamic Voltage Scaling for minimizing energy consumption in an embedded system processor while maintaining rea...
ERSA
2006
13 years 9 months ago
2006
- In this paper, we present a prototype FPGA design for an efficient physical layer implementation of a MIMO-OFDM technique. We propose a pipelined architecture using a Fast Fourie...