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» Energy exploration and reduction of SDRAM memory systems
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MICRO
1997
IEEE
139views Hardware» more  MICRO 1997»
13 years 11 months ago
The Filter Cache: An Energy Efficient Memory Structure
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occu...
Johnson Kin, Munish Gupta, William H. Mangione-Smi...
USENIX
2003
13 years 8 months ago
Design and Implementation of Power-Aware Virtual Memory
Despite constant improvements in fabrication technology, hardware components are consuming more power than ever. With the everincreasing demand for higher performance in highly-in...
Hai Huang, Padmanabhan Pillai, Kang G. Shin
DATE
2005
IEEE
107views Hardware» more  DATE 2005»
14 years 1 months ago
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique
Complex applications implemented as Systems on Chip (SoCs) demand extensive use of system level modeling and validation. Their implementation gathers a large number of complex IP ...
César A. M. Marcon, Ney Laert Vilar Calazan...
VLSID
2007
IEEE
206views VLSI» more  VLSID 2007»
14 years 7 months ago
MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
CODES
2002
IEEE
14 years 12 days ago
Energy savings through compression in embedded Java environments
Limited energy and memory resources are important constraints in the design of an embedded system. Compression is an useful and widely employed mechanism to reduce the memory requ...
Guangyu Chen, Mahmut T. Kandemir, Narayanan Vijayk...