Sciweavers

185 search results - page 28 / 37
» Energy-oriented compiler optimizations for partitioned memor...
Sort
View
DAC
2010
ACM
13 years 8 months ago
Instruction cache locking using temporal reuse profile
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
Yun Liang, Tulika Mitra
PPOPP
2010
ACM
14 years 2 months ago
An adaptive performance modeling tool for GPU architectures
This paper presents an analytical model to predict the performance of general-purpose applications on a GPU architecture. The model is designed to provide performance information ...
Sara S. Baghsorkhi, Matthieu Delahaye, Sanjay J. P...
CGO
2003
IEEE
14 years 1 months ago
Addressing Mode Selection
Many processor architectures provide a set of addressing modes in their address generation units. For example DSPs (digital signal processors) have powerful addressing modes for e...
Erik Eckstein, Bernhard Scholz
24
Voted
DAC
2004
ACM
14 years 8 months ago
Data compression for improving SPM behavior
Scratch-pad memories (SPMs) enable fast access to time-critical data. While prior research studied both static and dynamic SPM management strategies, not being able to keep all ho...
Ozcan Ozturk, Mahmut T. Kandemir, I. Demirkiran, G...
IPPS
2010
IEEE
13 years 5 months ago
Solving the advection PDE on the cell broadband engine
In this paper we present the venture of porting two different algorithms for solving the two-dimensional advection PDE on the CBE platform, an in-place and an outof-place one, and ...
Georgios Rokos, Gerassimos Peteinatos, Georgia Kou...