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IPPS
2007
IEEE
14 years 1 months ago
Model-Guided Empirical Optimization for Multimedia Extension Architectures: A Case Study
Compiler technology for multimedia extensions must effectively utilize not only the SIMD compute engines but also the various levels of the memory hierarchy: superword registers,...
Chun Chen, Jaewook Shin, Shiva Kintali, Jacqueline...
IEEEPACT
2000
IEEE
13 years 11 months ago
Region Formation Analysis with Demand-Driven Inlining for Region-Based Optimization
Region-based compilation repartitions a program into more desirable compilation units for optimization and scheduling, particularly beneficial for ILP architectures. With region-...
Tom Way, Ben Breech, Lori L. Pollock
LCTRTS
2007
Springer
14 years 1 months ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...
LCTRTS
2010
Springer
13 years 4 months ago
Compiler directed network-on-chip reliability enhancement for chip multiprocessors
Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, program...
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin,...
ISCAS
2002
IEEE
124views Hardware» more  ISCAS 2002»
13 years 12 months ago
Performance optimization of multiple memory architectures for DSP
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha