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ERSA
2010
153views Hardware» more  ERSA 2010»
13 years 4 months ago
VAPRES: A Customizable and Flexible Base Architecture for Partially Reconfigurable Systems
- Partial reconfiguration (PR) enhances traditional FPGA-based high-performance reconfigurable computing by providing additional benefits such as reduced area and memory requiremen...
Ann Gordon-Ross, Abelardo Jara-Berrocal
FCCM
2002
IEEE
126views VLSI» more  FCCM 2002»
14 years 14 days ago
Hyperspectral Image Compression on Reconfigurable Platforms
NASA’s satellites currently do not make use of advanced image compression techniques during data transmission to earth because of limitations in the available platforms. With th...
Thomas W. Fry, Scott Hauck
ASAP
2006
IEEE
147views Hardware» more  ASAP 2006»
13 years 9 months ago
Reconfigurable Shuffle Network Design in LDPC Decoders
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
Jun Tang, Tejas Bhatt, Vishwas Sundaramurthy
ERSA
2010
186views Hardware» more  ERSA 2010»
13 years 5 months ago
DAPR: Design Automation for Partially Reconfigurable FPGAs
Partial reconfiguration (PR) enhances traditional FPGA-based high-performance reconfigurable computing by providing additional benefits such as reduced area and memory requirements...
Shaon Yousuf, Ann Gordon-Ross
EH
2002
IEEE
112views Hardware» more  EH 2002»
14 years 14 days ago
Evolving Circuits in Seconds: Experiments with a Stand-Alone Board-Level Evolvable System
The purpose of this paper is twofold: first, to illustrate a stand-alone board-level evolvable system (SABLES) and its performance, and second to illustrate some problems that occ...
Adrian Stoica, Ricardo Salem Zebulum, Michael I. F...