In this paper we propose a partitioning-based placement algorithm for FPGAs. The method incorporates simple, but effective heuristics that target delay minimization. The placement...
This paper presents a technique for recovering the high level design of legacy software systems according to user defined architectural plans. Architectural plans are represented...
We describe a model-based construction of an online tester for black-box testing of implementation under test (IUT). The external behavior of the IUT is modeled as an output obser...
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
This report describes Dartmouth College’s approach and results for the 2007 TREC Legal Track. Our original plan was to use the Combination of Expert Opinion (CEO) algorithm [1],...