213 search results - page 38 / 43 » Engineering parallel applications with tunable architectures |
CODES
2005
IEEE
14 years 1 months ago
2005
IEEE
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
ISPASS
2006
IEEE
14 years 1 months ago
2006
IEEE
Applications in Computer Networks often require high throughput access to large data structures for lookup and classification. Many advanced algorithms exist to speed these searc...
EDO
2006
Springer
13 years 11 months ago
2006
Springer
Reflective middleware has been proposed as an effective way to enhance adaptability of component-oriented middleware architectures. To be effectively adaptable, the implementation...
MIDDLEWARE
2004
Springer
14 years 24 days ago
2004
Springer
This paper surveys a variety of subsystems designed to be the building blocks from which sophisticated infrastructures for ubiquitous computing are assembled. Our experience shows...
HPDC
2010
IEEE
13 years 7 months ago
2010
IEEE
Massively multicore processors, like, for example, Graphics Processing Units (GPUs), provide, at a comparable price, a one order of magnitude higher peak performance than traditio...