Sciweavers

67 search results - page 10 / 14
» Enhanced Code Compression for Embedded RISC Processors
Sort
View
CASES
2007
ACM
13 years 11 months ago
Fragment cache management for dynamic binary translators in embedded systems with scratchpad
Dynamic binary translation (DBT) has been used to achieve numerous goals (e.g., better performance) for general-purpose computers. Recently, DBT has also attracted attention for e...
José Baiocchi, Bruce R. Childers, Jack W. D...
CODES
2005
IEEE
14 years 1 months ago
Comparing the size of .NET applications with native code
Byte-code based languages are slowly becoming adopted in embedded domains because of improved security and portability. Another potential reason for their adoption is the reputati...
Roberto Costa, Erven Rohou
ICIP
2001
IEEE
14 years 9 months ago
Efficient fine granular scalable video coding
In this work we present an efficient fine granular scalable video compression scheme which supports a fast bit rate adaptation independent of the encoder. The proposed scheme gene...
Christian Buchner, Thomas Stockhammer, Detlev Marp...
RSP
2006
IEEE
120views Control Systems» more  RSP 2006»
14 years 1 months ago
A Case Study of Design Space Exploration for Embedded Multimedia Applications on SoCs
Embedded real-time multimedia applications usually imply data parallel processing. SIMD processors embedded in SOCs are cost-effective to exploit the underlying parallelism. Howev...
Isabelle Hurbain, Corinne Ancourt, François...
CODES
2008
IEEE
14 years 2 months ago
Static analysis of processor stall cycle aggregation
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
Jongeun Lee, Aviral Shrivastava