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» Enhanced leakage reduction Technique by gate replacement
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ISCAS
2006
IEEE
135views Hardware» more  ISCAS 2006»
14 years 1 months ago
Wide temperature spectrum low leakage dynamic circuit technique for sub-65nm CMOS technologies
A new circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power in domino logic circuits. PMOS-only sleep transistors ar...
Volkan Kursun, Zhiyu Liu

Publication
156views
13 years 1 months ago
Dynamic Virtual Ground Voltage Estimation for Power Gating
With the technology moving into the deep sub-100nm region, the increase of leakage power consumption necessitates more aggressive power reduction techniques. Power gating is a prom...
Hao Xu, Ranga Vemuri, Wen-Ben Jone
ISCAS
2008
IEEE
136views Hardware» more  ISCAS 2008»
14 years 1 months ago
"Green" micro-architecture and circuit co-design for ternary content addressable memory
—In this paper, an energy-efficient and high performance ternary content addressable memory (TCAM) are presented. It employs the concept of “green” microarchitecture and circ...
Po-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu, Wei Hw...
FPL
2009
Springer
106views Hardware» more  FPL 2009»
14 years 2 days ago
Low power techniques for Motion Estimation hardware
Motion Estimation (ME) is the most computationally intensive and the most power consuming part of video compression and video enhancement systems. In this paper, we propose a nove...
Caglar Kalaycioglu, Onur C. Ulusel, Ilker Hamzaogl...
DAC
2006
ACM
14 years 8 months ago
Gate sizing: finFETs vs 32nm bulk MOSFETs
FinFET devices promise to replace traditional MOSFETs because of superior ability in controlling leakage and minimizing short channel effects while delivering a strong drive curre...
Brian Swahn, Soha Hassoun