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JCIT
2007
63views more  JCIT 2007»
13 years 7 months ago
Optimizing Reaching Definitions Overhead in Queue Processors
Queue computers are a viable option for embedded systems design. Queue computers feature a dense instruction set, high parallelism, low hardware complexity. In this paper we propo...
Yuki Nakanishi, Arquimedes Canedo, Ben A. Abderaze...
DATE
2004
IEEE
114views Hardware» more  DATE 2004»
13 years 11 months ago
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
Zhong Wang, Xiaobo Sharon Hu
LCTRTS
2009
Springer
14 years 2 months ago
A compiler optimization to reduce soft errors in register files
Register file (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing c...
Jongeun Lee, Aviral Shrivastava
ACMSE
2007
ACM
13 years 11 months ago
Enhancing clustering blog documents by utilizing author/reader comments
Blogs are a new form of internet phenomenon and a vast everincreasing information resource. Mining blog files for information is a very new research direction in data mining. We p...
Beibei Li, Shuting Xu, Jun Zhang
SBACPAD
2008
IEEE
100views Hardware» more  SBACPAD 2008»
14 years 2 months ago
Selection of the Register File Size and the Resource Allocation Policy on SMT Processors
The performance impact of the Physical Register File (PRF) size on Simultaneous Multithreading processors has not been extensively studied in spite of being a critical shared reso...
Jesús Alastruey, Teresa Monreal, Francisco ...