This paper focuses on matching 1D structures by variational methods. We provide rigorous rules for the construction of the cost function, on the basis of an analysis of properties ...
A PAL-based logic block is the core of great majority of contemporary CPLD devices. The purpose of the paper is to present a new approach to multi-level synthesis for PAL-based CP...
In this paper, a new realization for logic functions, namely Reversible Programmable Logic Array (RPLA), has been proposed. The proposed realization has the advantage of regularit...
Ahsan Raja Chowdhury, Rumana Nazmul, Hafiz Md. Has...
-- We present a new heuristic algorithm for hazard-free minimization of two-level logic. On nearly all examples, the algorithm finds an exactly minimum-cost cover. It also solves s...
In this paper an algorithm is proposed for the synthesis and exact minimization of ESCT (Exclusive or Sum of Complex Terms) expressions for Boolean functions of up to seven comple...
Dimitrios Voudouris, Marinos Sampson, George K. Pa...