710 search results - page 17 / 142 » Estimating design time for system circuits |
DATE
2003
IEEE
14 years 21 days ago
2003
IEEE
Execution time estimation of software at source-level is nowadays a crucial phase of the system design flow, especially for portable devices and real-time systems. From a source-...
TII
2011
13 years 2 months ago
2011
Abstract—Software systems that do not meet their timing constraints can cause risks. In this work, we propose a comprehensive method for assessing the risk of timing failure by e...
CORR
2008
Springer
13 years 7 months ago
2008
Springer
This paper presents an analysis and system-level design of a capacitive harvester of vibration energy composed from a mechanical resonator, capacitive transducer and a conditioning...
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
CASES
2007
ACM
2007
ACM
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
13 years 11 months ago
Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters....