710 search results - page 19 / 142 » Estimating design time for system circuits |
ISVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
Formal verification has become an important step in circuit and system design. A prominent technique is Bounded Model Checking (BMC) which is widely used in industry. In BMC it i...
TCAD
2002
13 years 7 months ago
2002
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
ICC
2007
IEEE
14 years 1 months ago
2007
IEEE
— In an OFDM system, channel estimation can be considered as sampling the time-frequency response of the channel through a number of known pilot symbols placed across the time-fr...
ITC
2003
IEEE
14 years 20 days ago
2003
IEEE
An in-circuit diagnostic test structure triggered by a light pulse captures logic states on-chip with picosecond timing accuracy, and the results read out via a scan chain thus pr...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...