710 search results - page 94 / 142 » Estimating design time for system circuits |
158
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DAC
2006
ACM
16 years 6 months ago
2006
ACM
In this paper, a Triangularization Based Structure preserving (TBS) model order reduction is proposed to verify power integrity of on-chip structured power grid. The power grid is...
173
Voted
MICRO
2010
IEEE
15 years 3 months ago
2010
IEEE
Bias temperature instability, hot-carrier injection, and gate-oxide wearout will cause severe lifetime degradation in the performance and the reliability of future CMOS devices. Th...
158
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AIPS
1994
15 years 7 months ago
1994
Aimsof traditional planners had beenlimited to finding a sequenceof operators rather than finding an optimal or neax-optimalfinal state. Consequent]y, the performanceimprovementsy...
156
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DAC
2010
ACM
15 years 3 months ago
2010
ACM
The verification of large radio-frequency/millimeter-wave (RF/MM) integrated circuits (ICs) has regained attention for high-performance designs beyond 90nm and 60GHz. The traditio...
158
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DAC
2010
ACM
15 years 9 months ago
2010
ACM
With the ever-increasing transistor variability in CMOS technology, it is essential to integrate variation-aware performance analysis into the task allocation and scheduling proce...