501 search results - page 18 / 101 » Evaluating CMPs and Their Memory Architecture |
ASPLOS
2009
ACM
14 years 8 months ago
2009
ACM
To improve the performance of a single application on Chip Multiprocessors (CMPs), the application must be split into threads which execute concurrently on multiple cores. In mult...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Convergence of communication, consumer applications and computing within mobile systems pushes memory requirements both in terms of size, bandwidth and power consumption...
FPL
2000
Springer
13 years 11 months ago
2000
Springer
Abstract. This paper presents an innovative architecture for a reconfigurable device that allows single cycle context switching and single cycle random access to the unified on-chi...
SC
1995
ACM
13 years 11 months ago
1995
ACM
The Convex SPP-1000 is the first commercial implementation of a new generation of scalable shared memory parallel computers with full cache coherence. It employs a hierarchical s...
PDPTA
2004
13 years 9 months ago
2004
We present the MBRAM model for static evaluation of the performance of memory-bound programs. The MBRAM model predicts the actual running time of a memory-bound program directly fr...