501 search results - page 32 / 101 » Evaluating CMPs and Their Memory Architecture |
IPPS
1992
IEEE
13 years 11 months ago
1992
IEEE
This paper presents a hybrid shared memory architecture which combines the scalability of a multistage interconnection network with the contention reduction benefits of coherent c...
DAC
2012
ACM
11 years 10 months ago
2012
ACM
Diverse IP cores are integrated on a modern system-on-chip and share resources. Off-chip memory bandwidth is often the scarcest resource and requires careful allocation. Two of t...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract--Many shared-memory parallel systems use lockbased synchronization mechanisms to provide mutual exclusion or reader-writer access to memory locations. Software locks are i...
HPCA
2003
IEEE
14 years 8 months ago
2003
IEEE
Thread-level speculation provides architectural support to aggressively run hard-to-analyze code in parallel. As speculative tasks run concurrently, they generate unsafe or specul...
ICCD
2008
IEEE
14 years 4 months ago
2008
IEEE
— We use a novel virtualization-based approach for computer architecture performance analysis. We present a case study analyzing a hypothetical hybrid main memory, which consists...