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» Evaluating CMPs and Their Memory Architecture
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IPPS
2007
IEEE
14 years 1 months ago
Improving Scalability of OpenMP Applications on Multi-core Systems Using Large Page Support
Modern multi-core architectures have become popular because of the limitations of deep pipelines and heating and power concerns. Some of these multi-core architectures such as the...
Ranjit Noronha, Dhabaleswar K. Panda
CODES
2004
IEEE
13 years 11 months ago
A loop accelerator for low power embedded VLIW processors
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
Binu K. Mathew, Al Davis
MICRO
2006
IEEE
114views Hardware» more  MICRO 2006»
14 years 1 months ago
Authentication Control Point and Its Implications For Secure Processor Design
Secure processor architecture enables tamper-proof protection on software that addresses many difficult security problems such as reverse-engineering prevention, trusted computing...
Weidong Shi, Hsien-Hsin S. Lee
IPPS
1998
IEEE
13 years 12 months ago
Impact of Switch Design on the Application Performance of Cache-Coherent Multiprocessors
In this paper, the effect of switch design on the application performance of cache-coherent non-uniform memory access (CC-NUMA) multiprocessors is studied in detail. Wormhole rout...
Laxmi N. Bhuyan, Hu-Jun Wang, Ravi R. Iyer, Akhile...
MMNS
2000
101views Multimedia» more  MMNS 2000»
13 years 9 months ago
Traffic Management in Isochronets Networks
: This paper presents an evaluation of a traffic management mechanism for high speed networks called RDMA (Route Division Multiple Access), developed as part of the Isochronets, a ...
Kelvin Lopes Dias, José Augusto Suruagy Mon...