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» Evaluating CMPs and Their Memory Architecture
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SEUS
2009
IEEE
14 years 2 months ago
Towards Time-Predictable Data Caches for Chip-Multiprocessors
Future embedded systems are expected to use chip-multiprocessors to provide the execution power for increasingly demanding applications. Multiprocessors increase the pressure on th...
Martin Schoeberl, Wolfgang Puffitsch, Benedikt Hub...
RSP
2006
IEEE
102views Control Systems» more  RSP 2006»
14 years 1 months ago
Rapid Resource-Constrained Hardware Performance Estimation
In a hardware-software co-design environment, an application is partitioned into modules. Each module is then mapped either to software or to hardware. The mapping process is driv...
Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrish...
ISORC
2003
IEEE
14 years 28 days ago
Design of SMIL Browser Functionality in Mobile Terminals
SMIL is a markup language which enables us to describe multimedia contents. This paper proposes a design model of SMIL browser functionality for mobile terminals whose resources a...
Satoshi Hieda, Yoshinori Saida, Hiroshi Chishima, ...
IPPS
1999
IEEE
13 years 12 months ago
NWCache: Optimizing Disk Accesses via an Optical Network/Write Cache Hybrid
In this paper we propose a simple extension to the I/O architecture of scalable multiprocessors that optimizes page swap-outs significantly. More specifically, we propose the use o...
Enrique V. Carrera, Ricardo Bianchini
ASPDAC
1998
ACM
160views Hardware» more  ASPDAC 1998»
13 years 12 months ago
Synthesis of Power Efficient Systems-on-Silicon
We developed a new modular synthesis approach for design of low-power core-based data-intensive application-specific systems on silicon. The power optimization is conducted in th...
Darko Kirovski, Chunho Lee, Miodrag Potkonjak, Wil...