501 search results - page 78 / 101 » Evaluating CMPs and Their Memory Architecture |
ICS
2009
Tsinghua U.
14 years 2 months ago
2009
Tsinghua U.
Ethernet line rates are projected to reach 100 Gbits/s by as soon as 2010. While in principle suitable for high performance clustered and parallel applications, Ethernet requires ...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—During post-silicon processor debugging, we need to frequently capture and dump out the internal state of the processor. Since internal state constitutes all memory elements, th...
IEEEPACT
2006
IEEE
14 years 1 months ago
2006
IEEE
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...
SBACPAD
2006
IEEE
14 years 1 months ago
2006
IEEE
Performance evaluation of contemporary processors is becoming increasingly difficult due to the lack of proper frameworks. Traditionally, cycle-accurate simulators have been exte...
HPCA
1999
IEEE
13 years 12 months ago
1999
IEEE
This work presents and evaluates a novel processor microarchitecture which combines two paradigms: access/ execute decoupling and simultaneous multithreading. We investigate how b...