501 search results - page 82 / 101 » Evaluating CMPs and Their Memory Architecture |
DAC
2007
ACM
14 years 8 months ago
2007
ACM
Mapping packet processing applications onto embedded network processors (NP) is a challenging task due to the unique constraints of NP systems and the characteristics of network a...
HIPEAC
2009
Springer
14 years 2 months ago
2009
Springer
Developing streaming applications on heterogenous multi-processor architectures like the Cell is difficult. Currently, application developers need to know about hardware details t...
DATE
2010
IEEE
14 years 22 days ago
2010
IEEE
Abstract—Built-In Self-Test (BIST) is less often applied to random logic than to embedded memories due to the following reasons: Firstly, for a satisfiable fault coverage it may...
HPCA
1998
IEEE
13 years 12 months ago
1998
IEEE
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
TC
2010
13 years 6 months ago
2010
—The most pervasive compute operation carried out in almost all bioinformatics applications is pairwise sequence homology detection (or sequence alignment). Due to exponentially ...